FIG. 21 is a block diagram showing a conventional semiconductor memory device of such a structure that spare column and normal column can be discriminated in serial access cycles. In FIG. 21, a counter 1 outputs a counter output signal CO to a spare decoder 2 and a normal selector 4, respectively. The spare decoder 2 discriminates whether an address of the counter output signal CO is a spare address or not, and outputs a spare/normal discrimination signal SNJ to a spare selector 3 and the normal selector 4, respectively. On the basis of the spare/normal discrimination signal SNJ, the spare selector 3 outputs a spare column select signal SCSL. On the Other hand, on the basis of the spare/normal discrimination signal SNJ, the normal selector 4 outputs a normal column select signal NCSL. These spare column select signal SCSL and the normal column select signal NCSL are both given to memory cells to select a spare column or a normal column.
The operation of the device thus constructed will be described hereinbelow.
The counter 1 is activated on the basis of a clock signal applied from a clock signal generating circuit (not shown). Here, when the counter output signal CO is a spare address, the spare decoder 2 recognizes this spare address, and switches the spare/normal discrimination signal SNJ to a status where the spare discrimination is active. As a result, the spare selector 3 sets the spare column select signal SCSL to be active. On the other hand, the normal selector 4 sets the normal column select signal NCSL to be non-active. As a result, the memory cell (not shown) is switched from the defective column to the spare column.
On the other hand, when the counter output signal CO of the counter 1 is a normal address, the spare decoder 2 recognizes this normal address, and switches the spare/normal discrimination signal SNJ to a status where the normal discrimination is active. As a result, the spare selector 3 sets the spare column select signal SCSL to be non-active. On the other hand, the normal selector 4 sets the normal column select signal NCSL to be active. As a result, the normal column is selected in the memory cell (not shown) for use.
In the conventional semiconductor memory device as described above, three operational steps are required as follows: the counter output signal CO is outputted from the counter 1; this counter output signal CO is given to the spare decoder 2 to obtain the spare/normal discrimination signal SNJ; and on the basis of the spare/normal discrimination signal SNJ, the spare column select signal SCSL is outputted from the spare selector 3, or the normal column select signal NCSL is outputted from the normal selector 4. Consequently, it takes a long time to select the spare column or the normal column whenever the memory is accessed, thus raising a problem in that an access speed of the memory cells is relatively slow.